Dynamic random access memory (DRAM) cell size shrinkage may continue to occur due to improvements in process technology. Additionally, CPU (central processing unit) performance improvements may result in lower power consumption requirements, data bandwidth (BW) demands and capacity demands. DRAM cell refresh time requirements may also be getting shorter, while cell sizes continue to reduce in size. Accordingly, maintaining cell capacitance may be more difficult and cell leakage may increase due to a smaller two dimensional (2D) footprint. For example, larger DRAM capacities may demand an increase in the frequency at which the cells need to be refreshed to maintain the data stored in the cells, requiring more refresh time to maintain cell data for DRAMs, which may increase the potential for contention between refresh operations and read/write operations. As a result, performance degradations may occur.